Design of Interconnection Networks for Programmable Logic by Guy Lemieux

By Guy Lemieux

Programmable good judgment units (PLDs) became the major implementation medium for the majority of electronic circuits designed at the present time. whereas the highest-volume units are nonetheless outfitted with full-fabrication instead of box­ programmability, the craze in the direction of ever fewer ASICs and extra FPGAs is apparent. This makes the sector of PLD structure ever extra very important, as there's improved call for for quicker, smaller, more cost-effective and lower-power programmable good judgment. PLDs are ninety% routing and 10% common sense. This e-book makes a speciality of that ninety% that's the programmable routing: the way within which the programmable wires are hooked up and the circuit layout of the programmable switches themselves. someone trying to comprehend the layout of an FPGA must turn into lit­ erate within the complexities of programmable routing structure. This booklet builds at the cutting-edge of programmable interconnect through offering new equipment of investigating and measuring interconnect constructions, in addition to new programmable swap uncomplicated circuits. The early section of this e-book offers an exceptional survey of interconnec­ tion constructions and circuits as they exist this present day. Lemieux and Lewis then supply a brand new technique to layout sparse crossbars as they're utilized in PLDs, and exhibit that the strategy works with an empirical validation. this can be one in all a couple of routing structure works that hire analytical ways to take care of the routing archi­ tecture layout. The research allows fascinating insights now not mostly attainable with the normal empirical approach.

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IThe value of n2 is also arbitrary, but an upper bound is determined by the fanout pattern used. The upper bound for n2 is at least M(M + 1)-1. 5. Non-blocking Richards-Hwang network with full broadcast ability. Connecting Multiple PLDs: Partial Crossbar Structures A partial crossbar is a connection pattern proposed by Butts, Batcheller, and Vargese [BBV92, VBB93] for use in large-scale logic emulation systems. Such a system is composed of a large number of PLOs which are connected together to emulate a much larger circuit than can be implemented in any single PLO.

It is important that each of the PLDs in these large emulation systems are highly routable to avoid this time-consuming iteration. For example, there are 1728 Plasma PLDs [ACC+96] used in Teramac. The design goal was to completely place and route each PLD within 3 seconds. Plasma would have used full crossbars to guarantee this routability, but to save area it was necessary to use only 114 of the switches. Results in this chapter will show that sparse crossbars with a switch density of only 1128 achieve better routability than the switch pattern chosen for Teramac.

In these figures, SRAM bits are shown to represent the configuration state of the PLD. In practice, however, any memory technology can be used. The idea of clustering N BLEs into a CLB is explored in [BR97a]. Using a heuristic algorithm to pack lookup tables into fixed-size clusters, [BR97a] determines that architectures with N > 1 use less area than an unclustered architecture (N = O. In particular, clusters of size N = 4 are shown to require Models, Methodology and CAD Tools 29 10% fewer transistors.

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